Field of Invention
The present invention relates to a modeling method of a SPICE model series of a field effect transistor (FET), and specifically to a modeling method of a SPICE model series of a Silicon On Insulator (SOI) FET, belonging to the field of micro-electronic device modeling.
Description of Related Arts
A Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is a four-port semiconductor device, where different excitation is applied to each port, and a drain current of the device also changes accordingly. An input/output mathematical expression is obtained by establishing a mathematical model of the device, and circuit designers use the model to perform SPICE emulation of circuit design. Currently, multiple mathematical models with respect to the MOSFET are proposed, and each model includes a large number of parameters.
An SOI FET (also referred to as an MOSFET) generally has two application modes. In one application mode, a body leading-out structure (including T-shaped gate leading-out structure and an H-shaped gate leading-out structure) exists, and in the other application mode, no body leading-out structure (that is, a floating structure) exists. FIG. 1 is a schematic diagram of a layout of a device of a T-shaped gate leading-out structure. When a voltage is applied to a gate, a substrate below the T-shaped gate 102 is reversed to form a conductive channel. Currently, it is generally considered that the properties of the channel are completely consistent with those of a channel below a normal gate 101, so the T-shaped gate 102 is only equivalent to that an effective width of the device is increased. However, such a processing manner is extremely simple, and is even faulty in the current process. The device of a body leading-out structure may even present some characteristics that the model fails to cover.
The T-shaped gate 102 is not singly doped, where one half is doped with N-type impurities and the other half is doped with P-type impurities. The electrical properties of the T-shaped gate 102 are totally different from those of the singly doped normal gate 101. Moreover, when modeling (referred to establishing a SPICE model, the same below) is performed on the floating structure, model parameters, related to the body, of the device need to be extracted through a device of a body leading-out structure. If the leading-out part (that is, the conductive channel below the T-shaped gate 102) is not taken into consideration and test data of the device of a body leading-out structure is directly used to extract the model parameters, it is difficult for the established SPICE model of a floating structure to accurately express some properties of the device, and even a fault occurs during emulation.
In view of this, the present invention provides an accurate modeling method of a SPICE model series of an SOI FET, so as to more accurately and effectively model and emulate the SOl FET.